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W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
Features
* * * * * * * * * * * Intel PC SDRAM compalint 168 pins, dual in-line memory module (DIMM) Two memory rows on this module (Double Bank Module) Unbuffered DIMM Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8 and full page 4k refresh cycles/64ms Interface: LVTTL Serial Presence Detect with EEPROM Single 3.3V0.3V power supply PCB: height (1,375 mil) single sided component
Part Number
Module Part Number W9828BADA-8H W9828BADA-8N W9828BADA-10 Speed Grade PC100 CL=2 PC100 CL=3 PC66 CL=2, 3
General Description
The Winbond W9828BADA is a 16M x 64 Synchronous Dynamic RAM memory module. This module consists of sixteen pieces of W986408AH (8M x 8 bit) SDRAMs in 54-pin TSOP-II 400mil package and a 2K EEPROM in 8-pin SOP package on a 168-pin 6-layer PCB. One 0.1 uF and one 0.33uF decoupling capacitor is used for each SDRAM. The W9828BADA is a Dual In-line Memory Module for mounitng into 84-pin dual readout zigzag edge connector sockets. It is designed to operate in 3.3V memory systems.
Revision 0.9
1 OF 12
Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
Pin Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 VSS NC NC VDD WE# DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 CS0# NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CLK0 VSS NC CS2# DQM2 DQM3 NC VDD NC NC *CB2 *CB3 VSS DQ16 DQ17 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VDD DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC **SDA **SCL VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 *CB4 *CB5 VSS NC NC VDD CAS# DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1# RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 *A12 VSS CKE0 CS3# DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 VDD
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
FRONT 1 10 11 40 41 84
85
94 95
124 125 BACK
168
Revision 0.9
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Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
Pin Description
Pin CLKn CSn# CKEn A0~A11 BA0~BA1 RAS# CAS# WE# DQM0~7 DQ0~63 VDD VSS SCL SDA SAn NC Name Clock Inputs Chip select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Input/Output Mask Data Input/Output Power (+3.3 V) Ground Serial Clock Serial Data I/O SPD Address Line No Connection Function Description System clock used to sample inputs on the rising edge of clock. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self-Refresh mode is entered. Multiplexed pins for row and column address. Row address: A0~A11. Column address: A0~A8. Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Command input. When sampled at the rising edge of the clock, RAS#, CAS# and WE# define the operation to be executed. Referred to RAS# Referred to RAS# The output buffer is placed at Hi-Z when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write data. Multiplexed pins for data output and input Power for input buffers and logic circuit inside SDRAM. Ground for input buffers and logic circuit inside SDRAM. Clock for serial presence detection Data line for serial presence detection System assigned address (SA0~SA2) to identify different memory module in a system board. No connection
Revision 0.9
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Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
BLOCK DIAGRAM
CS0 CS1 DQM0 DQ (7:0)
10
U1
U20
DQM4 DQ (39:32)
10
U2
U19
DQM1 DQ (15:8)
10
U3
U18
DQM5 DQ (47:40)
10
U4
U17
CS2 CS3 DQM2 DQ (23:16)
10
U7
U14
DQM6 DQ (55:48)
10
U6
U15
DQM3 DQ (31:24)
10
U9
U12
DQM7 DQ (63:56)
10
U8
U13
VCC SERIAL PD
10K
SCL SDA SA2 SA1 SA0 U10 WP
47K
CKE1 CKE0 RAS CAS WE
SDRAM U12-15, 17-20 SDRAM U1-4, U6-9 SDRAM U1-4, 6-9, 12-15, 17-20 SDRAM U1-4, 6-9, 12-15, 17-20 SDRAM U1-4, 6-9, 12-15, 17-20 SDRAM U1-4, 6-9, 12-15, 17-20 SDRAM U1-4, 6-9, 12-15, 17-20 SDRAM U1-4, 6-9, 12-15, 17-20
One 0.33uF and One 0.1uF per SDRAM device
CLOCK WIRING CLOCK INPUT CLK0 CLK1 CLK2 CLK3 LOAD 4 SDRAMS + 3.3pF cap 4 SDRAMS + 3.3pF cap 4 SDRAMS + 3.3pF cap 4 SDRAMS + 3.3pF cap
A(11:0) BA(1:0) VDD
VSS
SDRAM U1-4, 6-9, 12-15, 17-20
Revision 0.9
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Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VIN, VOUT VDD TOPR TSTG
ITEM
Input, column Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current
RATING
-0.3~VCC+0.3 -0.3~4.6 0~70 -55~125 18 50
UNIT
V V C C W mA
NOTES
PD
IOUT
Note: Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70C )
SYMBOL VDD VIH VIL PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage MIN 3.0 2.0 -0.3 TYP 3.3 MAX 3.6 VCC+0.3 0.8 UNIT V V V NOTES
Note: VIH(max) = VDD +1.2V for pulse width < 5ns
VIL(min) = VSS -1.2V for pulse width < 5ns All voltages are referenced to VSS
CAPACITANCE (VCC=3.3V, Af = 1MHz, Ta=25C)
PIN
Address(A0~A11, BA0~BA1) RAS#, CAS#, 1WE# CKE0, CKE1 CLK0, CLK1, CLK2, CLK3 CS0#, CS1#, CS2#, CS3# DQM0~DQM7 DQ0~DQ63
SYMBOL
Cadd Ccmd CCKE CCLE CCS CDQM CIO
MIN
-
MAX
64 64 32 27.3
UNIT
pf pf pf pf pf pf pf
-
16 8 10
Revision 0.9
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Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
DC CHARACTERISTICS
(VCC = 3.3V 0.3V, Ta=0~70C)
SYMBOL ITEMS OPERATING CURRENT (tCK=min, tRC=min) Active Precharge command cycling without burst operation STANDBY CURRENT (tCK=min, CS#=VIH VIH/L=VIH(min)/VIL(max) Bank: inactive state) -8H/-8N MIN MAX -10 MIN MAX UNIT NOTES
ICC1
1 Bank Operation
1520
1280
mA
1, 3
ICC2 ICC2P ICC2S ICC2PS ICC3 ICC3P ICC4
CKE=VIH CKE=VIL (Power Down mode)
960 48 80 32 1200 128 2160
800 mA 48 80 mA 32 960 128 1920 mA mA mA 1, 3 1 1, 2, 3 1
ICC5 ICC6
STANDBY CURRENT CKE=VIH (CLK=VIL, CS#=VIH VIH/L=VIH(min)/VIL(max) CKE=VIL (Power BANK: inactive state) Down mode) NO OPERATING CKE=VIH CURRENT (tCK=min, CS#=VIH(min) CKE=VIL (Power BANK: active state (4 Down mode) banks)) BURST OPERATING CURRENT (tCK=min, CS#=VIH(min), Read/Write command cycling) AUTO REFRESH CURRENT (tCK=min, tRC=min, Auto Refresh command cycling SELF REFRESH CURRENT (Self Refresh mode CKE=0.2V)
1680 32
1440 32
mA mA
1, 3
Note: 1. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC. 2. These parameters depend on the output loading. The specified values are obtained with output open 3. These valuse are measured under the following conditions Front(or back): Under the measuring conditions given on the data sheet Back(or front): In stand by (measured under the ICC2 conditions)
Revision 0.9
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Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
AC CHARACTERISTICS AND OPERATING CONDITION
( Vcc=3.3V0.3V, Ta=0 to 70C )
SYMBOL tRC tRAS tRCD tCCD tRP tRRD tWR tCK tCH tCL tAC tOH tHZ** tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC PARAMETER Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b)Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time CL*=2 CL*=3 CLK Cycle Time CL*=2 CL*=3 CLK High Level CLK Low Level Access Time from CLK CL*=2 CL*=3 Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time -8H MIN 68 48 20 1 20 20 10 8 10 8 3 3 6 6 3 3 0 0 0.5 2 1 2 1 2 1 2 1 16 8 8 10 3 3 0 0 0.5 2 1 2 1 2 1 2 1 16 MAX 100000 MIN 72 48 20 1 20 20 12 10 12 10 3 3 -8N MAX 100000 MIN 90 60 30 1 30 20 15 10 15 10 3 3 -10 MAX 100000 UNIT ns cycle ns
1000 1000
1000 1000
7 6 8 8 10 3 3 0 0 0.5 3 1 3 1 3 1 3 1 20
9 8 10 10 10
64
64
64
ms ns
Note: *CL= CAS Latency
** tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. Refer to the individual component
Revision 0.9
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Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
AC TESTING CONDITIONS
Output Timing Measurement Reference Level Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signal Input Reference Level 1.4V/1.4V See diagram B Below 2.4V/0.4V 2ns 1.4V
3.3 V
1.4 V
1.2K
50 ohms
output 50pF 0.87K
output
Z = 50 ohms 50pF
AC TEST LOAD (A)
Note: Transition times are measured between VIH and VIL.
AC TEST LOAD (B)
Revision 0.9
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Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.
Table 1: Truth Table
COMMAND Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect Auto-Refresh Self-Refresh Entry Self Refresh Exit Clock suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Data write/Output Enable Data Write/Output Disable Device state Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle idle (S.R.) Active Idle Active (5) Active Any (power down) Active Active
( note (1), (2))
CKEn-1 H H H H H H H H H H H H H L L H H H L L L H H CKEn X X X X X X X X X X X H L H H L L L H H H X X DQM X X X X X X X X X X X X X X X X X X X X X L H BA0, BA1 V V X V V V V V X X X X X X X X X X X X X X X A10 V L H L H L H V X X X X X X X X X X X X X X X A11, A9-0 V X X V V V V V X X X X X X X X X X X X X X X ___ CS L L L L L L L L L L H L L H L X H L X H L X X ___ RAS L L L H H H H L H H X L L X H X X H X X H X X ___ CAS H H H L L L L L H H X L L X H X X H X X H X X ___ WE H L L L L H H L H L X H H X X X X X X X X X X
Notes:
(1) V=Valid X=Don't care L=Low Level H=High Level (2) CKEn signal is input level when commands are provided. (3) These are state of bank designated by BA0, BA1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode
Revision 0.9
9 OF 12
Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
Serial Presence Detect EEPROM
The Serial Presence Detect (SPD) function is implemented using a 2,408-bit EEPROM component. This nonvolatile storage device contains data for identifying the module type and various SDRAM organization and timing parameters. System read operations to the EEPROM device occur using the DIMM SCL(clock) and SDA (data) signals, together with SA(2:0) which provide the EEPROM Device Address.
SPD EEPROM DC OPERATING CONDITIONS
(Vcc=3.3V0.3V)
PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (logic 0) Voltage, all inputs OUTPUT LOW VOTAGE, lout=3 Ma INPUT LEAKGE CURRENT, Vin =GND to Vcc OUTPUT LEAKAGE CURRENT, VOUT=GND to Vcc STANDBY CURRENT SCL=SDA Vcc-0.3V, All other inputs=GND or 3.3V +10% POWER SUPPLY CURRENT SCL clock frequency = 100KHz SYMBOL VCC VIH VIL VOL ILI ILO ISB ICC MIN 3.0 VCCx.7 -0.3 MAX 3.6 VCC+ .5 VCCx.3 0.4 1 1 10 1 UNIT V V V V uA uA uA mA NOTES
IOL=3mA
SPD AC OPERATING CONDITIONS
(Vcc=3.3V0.3V)
AC CHRARCTERICS SYMBOL SCL clock frequency fSCL Noise Suppression Time Constant at SCL,SDA Inputs tI SCL Low to SDA Data Out Valid tAA Time the bus must be free before a new transition can start tBUF Start Condition Hold Time tHD:STA Clock Low Period tLOW Clock High Period tHIGH Start Condition Setup Time tSU:STA Data in Hold Time tHD:DAT Data in Setup Time tSU:DAT SDA and SCL Rise time tR SDA and SCL Fall Time tF Stop Condition Setup Time tSU:STO Data Out Hold Time tDH Write Cycle Time tWR PARAMETER MIN MAX 100 100 3.5 UNIT KHz ns us us us us us us us ns us ns us ns ms NOTES
0.3 4.7 4.0 4.7 4.0 4.7 0 250
1 300 4.7 300 15
Note:
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled, SDA is allowed to remain high the bus level pull-up resistor, and the device does not respond to its slave address.
Revision 0.9
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Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
CONTENTS OF EEPROM (SPD Versions 1.2)
Byte Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-125 126 127 128+ FUNCTION DESCRIBED Defines # bytes written into serial memory at module manufacturer Total # bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM..) # Row Addresses on this assembly # Column Addresses on this assembly # Module Rows on this assembly Data Width of this assembly.. ..Data Width continuation Voltage interface standard of this assembly SDRAM Cycle time @CAS latency of 3 SDRAM Access time form clock @CAS latency of 3 DIMM Configuration type (Non-parity, Parity ECC) Refresh Rate/Type SDRAM width , Primary DRAM Error Checking SDRAM data width Minimum Clock Delay, Back Random Column Addresses Burst Lengths supported #Bank on Each SDRAM device CAS# Latencies Supported CS# Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM cycle time @CAS latency of 2 SDRAM access time form clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Precharge to active command period (tRP) Active to Active command period (tRRD) Active to Read/Write command delay time(tRCD) Minimum Active to precharge period (tRAS) Density of each Row on Module Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time Data signal input hold time Superset Information(may be used in future) SPD Revision Checksum for Bytes 0-62 Manufacturers code Manufacturing location Manufacturer's Part Number Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data System frequency for 100 MHz Intel Specification details Unused storage locations FUNCTION SUPPORTED -8H -8N 128 bytes 256 bytes (2K- bit) SDRAM 12 9 2 row 64 bits LVTTL 8ns 10ns 10ns 6ns 6ns 8ns Non parity 15.625 us, support self refresh X8 None TCCD =1 CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Non-buffered Non -registered & redundant addressing +/-10% voltage tolerance , Burst Read, Single bit Write, precharge all, auto precharge 10ns 12ns 15ns 6ns 6ns 9ns 20ns 20ns 30ns 20ns 20ns 20ns 20ns 20ns 30ns 48ns 48ns 60ns 2 row of 64MB . 2ns 2ns 3ns 1ns 2ns 2ns 3ns 1ns Current release Intel spd 1.2 -10 -8H HEX VALUE -8N 80h 08h 04h 0Ch 09h 02h 40h 00h 01h A0h 60h 00h 80h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh A0h 60h 00h 00h 14h 14h 14h 30h 20h 20h C0h 60h 00h 00h 14h 14h 14h 30h 10h 20h 10h 20h 10h 00h 12h 24h MFG Dep MFG Dep MFG Dep MFG Dep MFG Dep MFG Dep MFG Dep 64h F5h FFh F0h 90h 00h 00h 1Eh 14h 1Eh 3Ch 30h 30h -10
80h 60h
A0h 80h
E4h
E4h
100MHz 66MHz Detailed 100MHz Information
F7h
66h 06h
Revision 0.9
11 OF 12
Publication Release Date:98/05/18
W9828BADA 128MB (16M x 64) PC100 SDRAM MODULE
PACKGE DIMENSIONS
Units:Inches
5.250 5.014
R 0.079 0.157 .004
1.375
0.118
0.350 .118DIA .004
0.250 1.450
0.250
0.450
2.150
0.250
0.250
0.123
.005
0.123
.005
0.079 .004
0.079
.004
Detail A
Detail B
0.039
.002 0.170 Max 0.010 Max
0.100 Min
0.050 Detail C 0.050 .0039
Tolerances: .005 unlesss othrerwise specified The used device is 8M*8 SDRAM,TSOP
Revision 0.9
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Publication Release Date:98/05/18
0.118 Min
A
B
C
0.700

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